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complete cmos stereo audio input and output system featuring: delta-sigma a/d and d/a converters using 64x oversampling. input anti-aliasing and output smoothing filters. programmable input gain (0 db to 22.5 db). programmable output attenuation (0 db to 46.5 db). sample frequencies from 4 khz to 50 khz. low distortion, thd < 0.02% for dac. thd < 0.02% for adc. low power dissipation: 80 ma typical. power-down mode : 1 ma typical. pin compatible with cs4216 when used in serial modes 3 and 4 (see appendix a). i 2 s(tm) compatible serial mode (sm5). operates from 5v or 3.3v digital power supply. requires 5v analog power supply. general description the cs4218 stereo audio codec is a monolithic cmos device for computer multimedia, automotive, and portable audio applications. it performs a/d and d/a conversion, filtering, and level setting, creating 4 audio inputs and 2 audio outputs for a digital computer system. the digital interfaces of left and right channels are multiplexed into a single serial data bus with word rates up to 50 khz per channel. adcs and the dacs use delta-sigma modulation with 64x oversampling. the adcs and dacs include digi- tal decimation filters and output smoothing filters on-chip which eliminate the need for external anti-alias- ing filters. the cs4218 is pin and function compatible with the cs4216 when used in serial modes 3 and 4. see the appendix a at the end of this data sheet for details. i 2 s is a trademark of philips. ordering information: CS4218-KL 0 to 70 c 44-pin plcc cs4218-kq 0 to 70 c 44-pin tqfp 16-bit stereo audio codec cs4218 ssync lout rout digital filters serial interface control digital filters input mux voltage reference clkin mf7:sfs1/f2 mf8:sfs2/f3 sdin sdout sclk smode1 reset refgnd refbyp refbuf lin1 lin2 rin1 rin2 vd va dgnd agnd a/d a/d d/a d/a do1 mf5:do2/int mf2:f2/cdin mf1:f1/cdout di1 mf6:di2/f1 mf3:di3/f3/cclk output mute output attenuation input gain pdn smode2 smode3 power control filt mf4:ma/ccs sep 96 ds135f1 1 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com copyright ? crystal semiconductor corporation 1996 (all rights reserved)
contents description cover . . . . . . . . . . . . . . . . . . . . 1 contents . . . . . . . . . . . . . . . . . . . 2 recommended operating conditions . . . . . . . . . . . . 3 analog input characteristics . . . . . . . . . . . . . . 3 analog output characteristics . . . . . . . . . . . . . 4 switching characteristics . . . . . . . . . . . . . . . 5 digital characteristics . . . . . . . . . . . . . . . . 7 a/d decimation filter characteristics . . . . . . . . . . . . 8 d/a interpolation characteristics . . . . . . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . 8 filter response plots . . . . . . . . . . . . . . . . 9 typical connection diagram . . . . . . . . . . . . . . 11 overview . . . . . . . . . . . . . . . . . . . 12 functional description . . . . . . . . . . . . . . . 12 - analog inputs and outputs . . . . . . . . . . . . . 12 - offset calibration . . . . . . . . . . . . . . . 13 - input gain and output level setting . . . . . . . . . . 13 - muting and the adc valid counter . . . . . . . . . . . 13 - parallel digital i/o pins . . . . . . . . . . . . . . 13 - reset and power down modes . . . . . . . . . . . . 13 - audio serial interface . . . . . . . . . . . . . . 14 serial interface modes . . . . . . . . . . . . . . . 15 - serial mode 3 . . . . . . . . . . . . . . . . 15 - serial mode 4 . . . . . . . . . . . . . . . . 22 - serial mode 5 . . . . . . . . . . . . . . . . 25 power supply and grounding . . . . . . . . . . . . . . 26 pin diagrams and descriptions . . . . . . . . . . . . . 29 package information . . . . . . . . . . . . . . . . 35 parameter definitions . . . . . . . . . . . . . . . . 36 appendix a: cs4218 compatibility with the cs4216 . . . . . . . . 38 appendix b: applications of serial mode 4 (sm4) . . . . . . . . 40 appendix c: setting clkin/sclk ratio for desired sample rate . . . . 43 cs4218 2 ds135f1
analog characteristics ( t a = 25 c; va, vd = +5v; input levels: logic 0 = 0v, logic 1 = vd; 1khz input sine wave; clkin = 12.288 mhz; sm3 slave sub-mode, 256 bpf; 0db gain/attenu- ation;conversion rate = 48 khz; sclk = 12.288 mhz; measurement bandwidth is 10 hz to 20 khz; unless oth- erwise specified.) parameter * symbol min typ max units analog input characteristics - minimum gain setting (0 db); unless otherwise specified. adc resolution 16 - - bits adc differential nonlinearity (note 1) - - 0.9 lsb instantaneous dynamic range (note 3) idr 80 84 - db total harmonic distortion thd - - 0.02 % interchannel isolation - 80 - db interchannel gain mismatch - - 0.5 db frequency response (note 1) -0.5 - +0.2 db programmable input gain - 22.5 - db gain step size - 1.5 - db absolute gain step error - - 0.75 db gain drift (note 1) - 100 - ppm/ c offset error 0db gain - - 50 lsb 22.5db gain - - 500 lsb full scale input voltage 2.5 2.8 3.1 v pp input resistance (notes 1,2) 20 - - k w input capacitance (note 1) - - 15 pf notes: 1. this specification is guaranteed by characterization, not production testing. 2. input resistance is for the input selected. non-selected inputs have a very high (>1m w ) input resistance. 3. operation in slave sub-modes may yield results lower than the 80 db minimum. * parameter definitions are given at the end of this data sheet. specifications are subject to change without notice. recommended operating conditions (agnd, dgnd = 0v, all voltages with respect to 0v.) parameter symbol min typ max units power supplies: digital vd 4.75 5.0 5.25 v digital (low voltage) vd 3.0 3.3 3.6 v analog va 4.75 5.0 5.25 v operating ambient temperature t a 02570 c cs4218 ds135f1 3
analog characteristics (continued) parameter * symbol min typ max units analog output characteristics - minimum attenuation; unless otherwise specified. dac resolution 16 - - bits dac differential nonlinearity (note 1) - - 0.9 lsb total dynamic range tdr - 93 - db instantaneous dynamic range idr 80 83 - db total harmonic distortion (note 4) thd - - 0.02 % interchannel isolation (note 4) - 80 - db interchannel gain mismatch - - 0.5 db frequency response (note 1) -0.5 - +0.2 db programmable attenuation (note 5) - -46.5 - db attenuation step size (note 5) - 1.5 - db absolute attenuation step error (note 5) - - 0.75 db gain drift (note 1) - 100 - ppm/ c refbuf output voltage (note 6) 1.9 2.1 2.3 v maximum output current= 400 m a offset voltage (note 7) - 10 - mv full scale output voltage (note 4) 2.4 2.7 3.1 v pp external load impedance 10k - - w internal resistor value for lout and rout 400 600 800 w deviation from linear phase (note 1) - - 1 degree out of band energy (22 khz to 100 khz) - -60 - db power supply power supply current (note 8) operating (vd = 5.0v) - 80 100 ma operating (vd = 3.3v) - 65 85 ma power down - - 1 ma power supply rejection (1 khz) - 40 - db notes: 4. 10 k w , 100 pf load. 5. tested in sm3, slave sub-mode, 256 bpf. 6. refbuf load current must be dc. to drive dynamic loads, refbuf must be buffered. ac variations in refbuf current may degrade adc and dac performance. 7. no dc load. 8. typical current: va = 30ma, vd = 50ma with vd = 5.0v. va = 30ma, vd = 35ma with vd = 3.3v. power supply current does not include output loading. * parameter definitions are given at the end of this data sheet. cs4218 4 ds135f1
switching characteristics (t a = 25 c; va, vd = +5v, outputs loaded with 30 pf; input levels: logic 0 = 0v, logic 1 = vd) parameter symbol min typ max units input clock (clkin) frequency sm3 multiplier mode clkin 64 768 800 khz sm3 master and slave modes, sm4, sm5 clkin 1.024 12.288 12.8 mhz clkin low time t ckl 15 - - ns clkin high time t ckh 15 - - ns sample rate (note 1) fs 4 - 50 khz di pins setup time to sclk edge (note 1) t s2 10 - - ns di pins hold time from sclk edge (note 1) t h2 8- -ns do pins delay from sclk edge t pd2 - - 30 ns sclk and ssync output all master modes (note 1) t pd3 - - 50 ns delay from clkin rising sclk period all master modes (notes 1,7) t sckw - 1/(fs*bpf) - s slave mode 75 - - ns sclk high time slave mode t sckh 30 - - ns sclk low time slave mode t sckl 30 - - ns sdin, ssync setup time to sclk edge slave mode t s1 15 - - ns sdin, ssync hold time from sclk edge slave mode t h1 10 - - ns sdout delay from sclk edge t pd1 - - 28 ns output to hi-z state bit 64 (note 1) t hz - - 12 ns output to non-hi-z bit 1 (note 1) t nz 15 - - ns reset pulse width low 500 - - ns ccs low to cclk rising sm4 (note 1) t cslcc 25 - - ns cdin setup to cclk falling sm4 (note 1) t discc 15 - - ns cclk low to cdin invalid (hold time) sm4 (note 1) t ccdih 10 - - ns cclk high time sm4 (note 1) t cclhh 25 - - ns cclk low time sm4 (note 1) t cclhl 25 - - ns cclk period sm4 (note 1) t cclkw 75 - - ns cclk rising to cdout data valid sm4 (note 1) t ccdov - - 30 ns cclk rising to cdout hi-z sm4 (note 1) t ccdot - - 30 ns cclk falling to ccs high sm4 (note 1) t cccsh 0- -ns reset low time prior to pdn rising trph 100 - - ns reset low hold time after pdn rising trhold 50 - - ms notes: 7. when the cs4218 is in master modes (ssync and sclk outputs), the sclk duty cycle is 50%. the equation is based on the selected sample frequency (fs) and the number of bits per frame (bpf). cs4218 ds135f1 5
t nz bit 1 bit 2 bit 1 bit 2 t sckw t sckh t sckl t h1 t s1 t s1 t h1 sclk [sm3,sm4\ ssync [sm3,sm4\ sdin sdout t pd1 t pd1 [sm3] (sm4) [sm3] (sm4) t hz bit 63 bit 64 bit 63 bit 64 (bit 32) (bit 31) (bit 31) (bit 32) bit 33 bit 33 (bit 1) (bit 1) bit 32 (bit 32) bit 32 (bit 32) serial audio port timing mf3:cclk mf1:cdout mf2:cdin mf4:ccs t ccdov 0msk do1 t ccdih t discc 123 5 89 467 10 adv lcl 11 latt4 latt3 latt2 latt1 latt0 ratt4 ratt3 ratt2 t cclkl t cclkh t cslcc t cclkw mf3:cclk mf1:cdout mf2:cdin mf4:ccs t ccdot 24 28 29 32 31 30 27 26 25 23 22 rgain2 rgain1 0 0 1 rgain0 err1 err0 lcl rcl di1 0 0 0 0 0 00 0 adv t cccsh serial mode 4. control data serial port timing cs4218 6 ds135f1
digital characteristics (t a = 25 c; va = 5v, vd = 5v or 3.3v) parameter symbol min typ max units high-level input voltage v ih 2.0 - vd+0.3 v low-level input voltage v il -0.3 - 0.8 v high-level output voltage at i 0 = -2.0 ma v oh vd-0.3 - - v low-level output voltage at i 0 = +2.0 ma v ol --0.2v input leakage current (digital inputs) - - 10 m a output leakage current (high-z digital outputs) - - 10 m a output capacitance (note 1) c out - - 15 pf input capacitance (note 1) c in - - 15 pf sclk t s2 t h2 t pd2 dix dox di/do timing clkin t ckl sclk sclk & ssync output timing ssync t ckh t pd3 (master mode) (master mode) t rhold pdn reset t rph power down mode timing cs4218 ds135f1 7
a/d decimation filter characteristics parameter symbol min typ max units passband 0 - 0.40fs hz frequency response -0.5 - +0.2 db passband ripple (0-0.4fs) - - 0.1 db transition band 0.40fs - 0.60fs hz stop band 0.60fs - - hz stop band rejection 74 - - db group delay - 8/fs s group delay variation vs. frequency - 0.0 m s d/a interpolation filter characteristics parameter symbol min typ max units passband 0 - 0.40fs hz frequency response -0.5 - +0.2 db passband ripple (0-0.4fs) - - 0.1 db transition band 0.40fs - 0.60fs hz stop band 0.60fs - - hz stop band rejection 74 - - db group delay - - 8/fs s group delay variation vs. frequency - - 0.1/fs m s absolute maximum ratings (agnd, dgnd = 0v, all voltages with respect to 0v.) parameter symbol min typ max units power supplies: digital vd -0.3 - 6.0 v analog va -0.3 - 6.0 v input current (except supply pins) - - 10.0 ma analog input voltage -0.3 - va+0.3 v digital input voltage -0.3 - vd+0.3 v ambient temperature (power applied) -55 - +125 c storage temperature -65 - +150 c warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. cs4218 8 ds135f1
0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70 input frequency ( fs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 magnitude (db) figure 6. cs4218 dac transition band 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 input frequency ( fs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 magnitude (db) figure 4. cs4218 dac frequency response 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 input frequency ( fs) -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -0.0 0.1 0.2 magnitude (db) figure 2. cs4218 adc passband ripple 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 input frequency ( fs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 magnitude (db) figure 1. cs4218 adc frequency response 0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70 input frequency ( fs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 magnitude (db) figure 3. cs4218 adc transition band 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 input frequency ( fs) -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -0.0 0.1 0.2 magnitude (db) figure 5. cs4218 dac passband ripple cs4218 ds135f1 9
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 input frequency ( fs) -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 phase (degrees) figure 7. cs4218 dac deviation from linear phase cs4218 10 ds135f1
0.1 m f 2.0 1 m f 0.1 m f + 24 4 va vd 23 5 +5v supply 1 m f + cs4218 agnd dgnd di1 do1 33 37 rin2 26 line in 2 right ferrite bead note: agnd and dgnd pins must be on the same ground plane + 40 k 40 k rout lout 15 16 refbyp 21 0.1 m f + 10 m f refgnd 22 + > 1.0 m f > 1.0 m f 0.0022 m f npo 0.0022 m f npo right audio output left audio output pdn sdout sclk ssync reset sdin 2 13 42 44 1 43 controller clkin 3 mf7:sfs1 mf8:sfs2 smode1 31 30 29 mode setting 32 smode2 41 smode3 lin2 28 line in 2 left rin1 25 line in 1 right refbuf 20 0.47 m f to optional input buffers lin1 27 line in 1 left +5v analog if a separate +5v analog supply is used, remove the 2.0 ohm resistor see analog inputs section for suggested input ciruits. refer to the analog inputs section for terminating unused line inputs. all other unused inputs should be tied to gnd. all nc pins should be left floating. mf3:di3/f3/cclk mf6:di2/f1 mf1:f1/cdout mf2:f2/cdin 36 35 34 40 39 38 mf5:do2/int mf4:ma/ccs parallel bits sub-mode or settings or control port filt required only for sm3 multiplier sub-mode 0.47 m f filt c 6 figure 8. typical connection diagram cs4218 ds135f1 11
overview the cs4218 contains two analog-to-digital con- verters, two digital-to-analog converters, adjustable input gain, and adjustable output level control. since the converters contain all the re- quired filters in digital or sampled analog form, the filters frequency responses track the sample rate of the cs4218. only a single-pole rc filter is required for the analog inputs and outputs. communication with the cs4218 is via a serial port, with separate pins for data input and out- put. the filters and converters operate over a sample rate range of 4 khz to 50 khz. functional description analog inputs and outputs figure 8 illustrates the suggested connection dia- gram for the cs4218. the line level inputs, lin1 or lin2 and rin1 or rin2, are selected by an internal input multiplexer. this multiplexer is a source selector and is not designed for real- time switching between inputs at the sample rate. when using the cs4218 as a drop-in replace- ment for the cs4216, existing recommended circuits (shown in the cs4216 data sheet) may be used as is without any noticeable degradation in performance. performance may vary with user-specific input circuits and should be checked when contemplating the use of cs4218 in existing cs4216 designs. unused analog inputs that are not selected have a very high input impedance, so they may be tied to agnd directly. unused analog inputs that are selected should be tied to agnd through a 0.1 m f capacitor. this prevents any dc current flow. the analog inputs are single-ended and inter- nally biased to the refbuf voltage (nominally 2.1 v). the refbuf output should be buffered if it is to be used for microphone phantom power. the use of a single-pole rc filter is recom- mended for use as an external anti-alias filter for the cs4218. the maximum cutoff frequency (lowpass) should not exceed 200 khz. a lower value for cuttoff frequency may be used, and is dependent upon the applications input band- width. the cs4218 inputs will accept a 1vrms signal, so a divide by two resistor network will serve as a front-end interface to 2 vrms line level sys- tems. figure 9 shows a simple input circuit that includes a gain of 0.5 and the required rc filter. the gain of 0.5 yields a full scale input sensitiv- ity of 2 v rms with the cs4218 programmable gain set to 0. the analog outputs are also single-ended and centered around the refbuf voltage. ac cou- pling capacitors of >1 m f are recommended. refer to figure 8 for the recommended analog output circuit. line in right line in left 300 pf npo npo 5.6k 0.33 uf lin1 or lin2 5.6k 5.6k 5.6k 0.33 uf 300 pf rin1 or rin2 figure 9. line inputs. cs4218 12 ds135f1
when using the cs4218 as a drop-in replace- ment for the cs4216, the external 600 ohm series resistors on lout and rout are not re- quired, since they are part of the cs4218 internal circuitry. in applications where both cs4218 and cs4216 are to be used, a board stuff option should be included in the bill of materials which will allow either a 600-ohm or a 0-ohm resistor to be used externally on both lout and rout. offset calibration both input and output offset voltages are mini- mized by internal calibration. offset calibration occurs after exiting a reset or power down condi- tion. during calibration, which takes 194 frames, output data from the adcs will be all zeros, and will be flagged as invalid. also, the dac out- puts will be muted. after power down mode or power up, reset should be held low for a minimum of 50 ms to allow the voltage refer- ence to settle. changing sample rates in master and slave modes automatically initiates a calibra- tion. input gain and output level setting input gain is adjustable from 0 db to +22.5 db in 1.5 db steps. output level attenuation is ad- justable from 0 db to -46.5 db in 1.5 db steps. both input and output gain adjustments are inter- nally made on zero-crossings of the analog signal, to minimize "zipper" noise. the gain change automatically takes effect if a zero cross- ing does not occur within 512 frames. muting and the adc valid counter the mute function allows the the user to turn off the output channels ( lout and rout ). prior to muting, the attenuation should be gradually ramped to maximum ( 46.5 db ), taking 1.5db steps. this significantly reduces any audible arti- facts that may be heard once muting is enabled. it is the users responsibility to program the serial host to perform the ramping. the serial data stream contains a "valid data" indicator, the adv bit, for the a/d converters which is low until enough clocks have passed since reset, or low-power (power down mode) operation to have valid a/d data from the filters (i.e., until calibration time plus the full latency of the digital filters has passed.) parallel digital input/output pins parallel digital inputs are general purpose pins whose values are reflected in the serial data out- put stream to the processor. parallel digital outputs provide a way to control external devices using bits in the serial data input stream. all par- allel digital pins, with the exception of di1 and do1, are multifunction and are defined by the serial mode selected. in serial mode 3 master modes and serial mode 5, two digital inputs and two digital outputs are available. in serial mode 3 slave modes, three digital inputs and two digi- tal outputs are available. in serial mode 4 only one digital input and digital output exists. fig- ure 10 shows when the di pins are latched, and when the do pins are updated. reset and power down modes reset places the cs4218 into a known state and must be held low for at least 50 ms after power- up or a hard power down. in reset, the digital outputs are driven low. reset sets all control data register bits to zero. changing sample rates in ssync sclk di pins latched do pins update start of frame (sm3) figure 10. digital input/output timing cs4218 ds135f1 13
master and slave modes automatically initiates a calibration. an rc filter with a time constant greater than 50 ms may be used on the reset pin. the cs4218 reset pin has hysterisis to ensure proper resets when using an rc filter. hard power down mode may be initiated by bringing the pdn pin low. all analog outputs will be driven to the refbuf voltage which will then decay to zero. all digital outputs will be driven low and then will go to a high imped- ance state. minimum power consumption will occur if clkin is held low. after leaving the power down state, reset should be held low for 50 ms to allow the analog voltage reference to settle before calibration is started. alternatively, soft power down may be initiated in slave modes by reducing the sclk frequency below the minimum values shown in table 1. in soft power down the analog outputs are muted and the serial data from the codec will indicate invalid data and the appropriate error code. the parallel bit i/o is still functional in soft power down mode. this is, in effect, a low power mode with only the parallel bit i/o unit functioning. audio serial interface in serial mode 3 (sm3), the audio serial port uses 4 pins: sdout, sdin, sclk and ssync. sdin carries the d/a converters input data and control bits. input data is ignored for frames not allocated to the selected cs4218. sdout car- ries the a/d converters output data and status bits. sdout goes to a high-impedance state during frames not allocated to the selected cs4218. sclk clocks data in to and out of the cs4218. ssync indicates the start of a frame and/or sub-frame. sclk and ssync must be synchronous to the master clock. serial mode 4 (sm4) is similar to sm3 with the exception of the control information. in serial mode 4, the control information is entered through a separate asynchronous control port. therefore, the audio serial port only contains audio data, which reduces the number of bits on the audio port from 64 to 32 per codec. this is useful for lower bit rate serial hosts. serial mode 5 (sm5) is compatible with the i 2 s tm serial data protocol. sm5 is a master mode only. as in sm3, 4 pins are used: sdout, sdin, sclk, and ssync. the serial port protocol is based on frames con- sisting of 1, 2, or 4 sub-frames. the frame rate is the system sample rate. each sub-frame is used by one cs4218 device. up to 4 cs4218s may be attached to the same serial control lines. sfs1 and sfs2 are tied low or high to indicate to each cs4218 which sub-frame is allocated for it to use. serial data format in sm3 and sm5, a sub-frame is 64 bits in length and consists of two 16-bit audio values and two 16-bit control fields. in sm4 a sub- frame is 32 bits in length and only contains the two 16-bit audio fields; the control data is loaded through a separate port. the audio data is msb bits per frame minimum sclk frequency for all modes except sm3 multiplier sub mode 32 clkin / 96 64 clkin / 48 128 clkin / 24 256 clkin / 12 sm3 multiplier sub mode 64 (16 * clkin) / 48 128 (16 * clkin) / 24 256 (16 * clkin) / 12 table 1. soft power down conditions (slave modes only) cs4218 14 ds135f1
first, 2s complement format. sub-frame bit as- signments are shown in figure 13. control data bits all reset to zero. cs4218 serial interface modes the cs4218 has three serial port modes, selected by the smode1, smode2 and smode3 pins. in all modes, clkin, sclk and ssync must be derived from the same clock source. sm3 was designed as an easy interface to general pur- pose dsps and provides features such as master and slave sub-modes and variable frame sizes. sm4 is similar to sm3 but splits the audio data from the control data thereby reducing the audio serial bus bandwidth by half. the control data is transmitted through a control serial port in sm4. sm5 is compatible with the i 2 s serial data proto- col. table 2 lists the three serial port modes avail- able, along with some of the differences between modes. the first three columns in table 2 select the serial mode. the "sclk bit center" column indicates whether sclk is rising or falling in the center of a bit period. the "sub-frame width" column indicates how many bits are in an individual codecs sub-frame. in sm3 and sm4, the number of bits per frame is program- mable. in all modes, sclk and ssync must be synchronous to the master clock. the last col- umn in table 2 lists the master frequencies used by the codec. in the sm3 multiplier sub-modes, the master clkin is multiplied internally by 16, so a 16xfs input clock must be provided. serial mode 3, (sm3) serial mode 3, master and slave sub-modes are enabled by setting smode3 = 0, smode2 = 1 and smode1 = 0. sm3 multiplier sub-modes are enabled by setting smode 3 = 0, smode 2 = 0, and smode 1 = 0. serial mode 3 is de- signed to interface easily to dsps. figure 11 illustrates the serial data in, sdin, sub-frame for all sm3 sub-modes. figure 12 also illustrates the serial data out, sdout, sub- frame for all sm3 sub-modes. figure 13 shows sub-frame bit definitions. in sm3 master sub-modes, mf5:do2 is a gen- eral purpose output and mf6:di2 is a general purpose input. the other six multifunction pins are used to select sub-modes under sm3. in sm3 slave sub-modes, mf3:f3 is configured as an additional general purpose input. sm3 is divided into four sub-modes, master (sm3-m), slave (sm3-s), multiplier master (sm3-mm), and multiplier slave (sm3-ms). sm3-m and sm3-s are identical to the cs4216 sm3 master and slave sub-modes, respectively. in sm3-m and sm3-mm sub-modes, the cs4218 generates ssync and sclk, while in sm3-s and sm3-ms sub-modes ssync and smode pins serial sclk bit sub-frame bits per sclk & master 3 2 1 mode center width frame (bpf) ssync frequency 0 0 0 sm3* falling 64 bits 64/128/256 master/slave clkin = 16xfs 0 0 1 sm5 rising 64 bits 64 master clkin = 256xfs 0 1 0 sm3 falling 64 bits 64/128/256 master/slave clkin or sclk = 256 fs 011 factory test mode 1 x x sm4 falling 32 bits ? 32/64/128 ? master/slave clkin = 256 fs ? contains audio data only. control information is entered through a separate serial port. * sm3 multiplier sub-modes. table 2. serial port modes cs4218 ds135f1 15
sclk must be generated externally. when the codec is the serial port master, the serial port sig- nal transitions are controlled with respect to the internal analog sampling clock to minimize the amount of digital noise coupled into the analog section. since ssync and sclk are externally derived when the codec slaves to the serial port, optimum noise management cannot be obtained; therefore, master modes should be used when- ever possible. multiplier sub-modes are identical to the sm3 modes except the master clock, clkin, is internally multiplied by 16. a 0.47 m f capacitor must be tied to the filt pin when using the multiplier sub-modes. master clock frequency in sm3-m and sm3-s sub-modes, the master clock, clkin, must be 256 fs max . for exam- ple, given a 48 khz maximum sample frequency, the master clock frequency must be 12.288 mhz. in sm3-mm and sm3-ms sub- modes, clkin must be 16xfs max . for example, given a 48 khz maximum sample fre- quency, the master clock frequency must be 768 khz. sclk and ssync must be synchro- nous to the master clock. sub-frame word b word a dac - left word 00 0 0 00 dac - right word do1 do2 00 msb lsb msb lsb mute isl isr lg3 lg2 lg1 lg0 rg3 rg2 rg1 rg0 la4 la3 la2 la1 la0 ra4 ra3 ra2 ra1 ra0 0 64 01 16 17 21 24 25 28 29 32 22 23 33 52 48 53 56 57 60 61 55 51 34 35 36 37 38 39 40 41 42 43 44 45 46 47 14 15 12 13 10 11 09 07 08 05 06 03 04 02 19 20 18 26 27 30 31 50 49 54 58 59 62 63 sub-frame figure 11. serial data input format - sm3, sm5. 64 sub-frame word b word a adc - left word 0 adc - right word di1 di2 x msb lsb adv lcl rcl msb lsb 00010000 01 16 17 21 24 25 28 29 32 22 23 33 52 48 53 56 57 60 61 55 0000 0000 51 34 35 36 37 38 39 40 41 42 43 44 45 46 47 14 15 12 13 10 11 09 07 08 05 06 03 04 02 19 20 18 26 27 30 31 50 49 54 58 59 62 63 er3 er2 er1 er0 ver3 ver2 ver1 ver0 di3 sub-frame figure 12. serial data output format - sm3, sm5. cs4218 16 ds135f1
sm3 and sm5 subframe bit definitions for sdin bit(s) symbol description bit(s) symbol description 1-16 dac-left audio data, dac left 2?s complement data, msb first (bit 1 = msb) 33-48 dac-right audio data, dac right 2?s complement data, msb first (bit 33 = msb) 17-21 unused unused, write with 0?s 49,50 unused unused, write with 0?s 22 mute mute dac outputs 0 = outputs on 1 = outputs muted 51 - 55 la4 - la0 left output attenuation 1.5db increments. 00000 = no atten. (0db) 11111 = 46.5db atten. 23 isl input mux, left select 0 = lin1 1 = lin2 56 - 60 ra4 - ra0 right output attenuation 1.5db increments. 00000 = no atten. (0db) 11111 = 46.5db atten. 24 isr input mux, right select 0 = rin1 1 = rin2 61 do1 digital output 1 0 = output low 1 = output high 25-28 lg3 - lg0 left input gain 1.5db increments. 0000 = no gain (0db) 1111 = 22.5 db gain 62 do2 digital output 2 0 = output low 1 = output high 29-32 rg3 - rg0 right input gain 1.5db increments. 0000 = no gain (0db) 1111 = 22.5 db gain 63,64 unused unused, write with 0?s sm3 and sm5 subframe bit definitions for sdout bit(s) symbol description bit(s) symbol description 1-16 adc-left audio data, adc left 2?s complement data, msb first (bit 1 = msb) 29-32 ver3-ver0 cs4218 version number 0000 = rev a 1000 = rev b and later 17-21 reserved these bits can be 0 or 1 33-48 adc-right audio data, adc right 2?s complement data, msb first (bit 33 = msb) 22 adv adc valid data 0 = invalid adc data 1 = valid adc data 49-60 reserved these bits can be 0 or 1 23 lcl adc left clipping 0 = normal 1 = clipping 61 di1 digital input 1 0 = input low 1 = input high 24 rcl adc right clipping 0 = normal 1 = clipping 62 di2 digital input 2 0 = input low 1 = input high 25-28 er3 - er0 error word 0000 = normal, no error 0001 = input sub-frame bit 21 set. control data is ignored. 0010 = sync pulse error outputs muted. 0011 = soft powerdown outputs muted. 63* di3 digital input 3 0 = input low 1 = input high * sm3-s sub-modes only 64 unused don?t care figure 13. sm3 / sm5 subframe, bit definitions cs4218 ds135f1 17
master sub-mode (sm3-m) master sub-mode is selected by setting mf4:ma = 1, which configures ssync and sclk as outputs from the cs4218. during power down, ssync and sclk are driven high impedance, and during reset they both are driven low. in master sub-mode the number of bits per frame determines how many codecs can occupy the serial bus and is illustrated in figure 14. bits per frame (master sub-modes) mf8:sfs2 selects the number of bits per frame. the two options are mf8:sfs2 = 1 which se- lects 128 bits per frame, and mf8:sfs2 = 0 which selects 64 bits per frame. selecting 128 bits per frame (mf8:sfs2 = 1) al- lows two cs4218s to operate from the same serial bus since each codec requires 64 bit peri- ods. the sub-frame used by an individual codec is selected using mf7:sfs1. mf7:sfs1 = 0 se- lects sub-frame 1 which is the first 64 bits following the ssync pulse. mf7:sfs1 = 1 se- lects sub-frame 2 which is the last 64 bits of the frame. selecting 64 bits per frame (mf8:sfs2 = 0) al- lows only one cs4218 to occupy the serial port. since there is only one sub-frame (which is equal to one frame), mf7:sfs1 is defined differ- ently in this mode. mf7:sfs1 selects the format of ssync. mf7:sfs1 = 0 selects an ssync pulse one sclk period high, directly preceding the data as shown in the center portion of fig- ure 14. this format is used for all other master and slave sub-modes in sm3. if mf7:sfs1 = 1, an alternate ssync format is chosen in which ssync is high during the entire word a (32 bits), which includes the left sample, and low for the entire word b (32 bits), which in- cludes the right sample. this alternate format for ssync is illustrated in the bottom portion of figure 14 and is only available in sm3-m and sm3-mm sub-modes with 64 bits per frame. a more detailed timing diagram for the 64 bits-per- frame master sub-modes is shown in figure 15. sample frequency selection (master sub-modes) in sm3-m and sm3-mm sub-modes, the multi- function pins mf1:f1, mf2:f2, and mf3:f3 are used to select the sample frequency divider. ta- ble 3 lists the decoding for the sample frequency select pins where the sample frequency selected is clkin/n. also shown are the sample fre- quencies obtained by using one of two example master clocks: either 12.288 mhz or 11.2896 mhz. changing sample frequency auto- matically initiates a calibration cycle. fs (khz) mf1: mf2: mf3: n with clkin or 16xclkin f1 f2 f3 12.288 11.2896 mhz mhz 0 0 0 256 48.00 44.10 0 0 1 384 32.00 29.40 0 1 0 512 24.00 22.05 0 1 1 640 19.20 17.64 1 0 0 768 16.00 14.70 1 0 1 1024 12.00 11.025 1 1 0 1280 9.60 8.82 1 1 1 1536 8.00 7.35 table 3. sm3-m/sm3-mm/sm5, fs select cs4218 18 ds135f1
sub-frame 1 sub-frame 2 frame (n+2) word a word b word a word b sub-frame 1 word a word b frame n 128 sclk periods sub-frame 2 word a word b frame (n+3) sub-frame 1 word a word b sub-frame 1 word a word b frame n 64 sclk periods sub-frame 1 word a word b frame (n+1) sub-frame 1 word a word b frame (n+2) sub-frame 1 word a word b frame (n+3) sub-frame 1 word a word b frame (n+4) sub-frame 1 word a word b frame n 64 sclk periods sub-frame 1 word a word b frame (n+1) sub-frame 1 word a word b frame (n+2) sub-frame 1 word a word b frame (n+3) sub-frame 1 word a word b frame (n+4) ssync data ssync data ssync data sfs2 sfs1 frame 1 1 0 1 mf8: mf7: sub- 1 2 sfs2 sfs1 frame 00 mf8: mf7: sub- 1 sfs2 sfs1 frame 01 mf8: mf7: sub- 1 figure 14. sm3-m and sm3-mm sub-modes. msb sclk ssync (mf7:sfs1=0) ssync (mf7:sfs1=1) msb 32 clocks 32 clocks lsb word a word b lsb sdin sdout figure 15. detailed sm3-m and sm3-mm sub-modes, 64 bpf. cs4218 ds135f1 19
slave sub-mode (sm3-s) in sm3, slave sub-mode is selected by setting mf4:ma = 0 which configures ssync and sclk as inputs to the cs4218. these two sig- nals must be externally derived from clkin. in sm3-s and sm3-ms sub-modes, the phase rela- tionship between sclk/ssync and clkin cannot be controlled since sclk and ssync are externally derived. therefore, the noise per- formance may be slightly worse than when using the master sub-modes. the number of sub-frames on the serial port is selected using mf1:f1 and mf2:f2. in sm3-s and sm3-ms sub-modes, mf3:f3 works as an additional general purpose input di3. figures 16 through 18 illustrate the sm3-s and sm3-ms sub-mode formats. bits per frame (slave sub-modes) in slave sub-modes, mf1:f1 and mf2:f2 select the number of bits per frame, which determines how many cs4218s can occupy one serial port. table 4 lists the decoding for mf1:f1 and mf2:f2. when set for 64 sclks per frame, one device occupies the entire frame; therefore, a sub-frame is equivalent to a frame. mf7:sfs1 and mf8:sfs2 must be set to zero. when set for 128 sclks per frame, two devices can occupy the serial port, with mf7:sfs1 se- lecting the particular sub-frame. mf8:sfs2 must be set to zero. see figure 17. when set for 256 sclks per frame (mf1:f1, mf2:f2 = 10), four devices can occupy the se- rial port. in this format both mf8:sfs2 and mf7:sfs1 are used to select the particular sub- frame. in all three of the above slave sub-mode formats, the frequency of the incoming sclk signal, in relation to the master clock provided on the clkin pin, determines the sample frequency. the cs4218 determines the ratio of sclk to clkin and sets the internal operating frequency accordingly. table 5 lists the sclk to clkin frequency ratio used to determine the codecs sample frequency. to obtain a given sample fre- quency, sclk must equal clkin divided by the number in the table, based on the number of bits per frame. as an example for sm3-s, as- suming 64 bpf (bits per frame) and clkin = 12.288 mhz, if a sample frequency of 24 khz is desired, sclk must equal clkin di- vided by 8 or 1.536 mhz. a change in sample rate automatically initiates a calibration cycle. when mf1:f1 = mf2:f2 = 1, sclk is used as the master clock and is assumed to be 256 times the sample frequency. in this mode, clkin is mf1: mf2: bits per sample frequency/ f1 f2 frame sclk 0 0 64 ratio to clkin sensed 0 1 128 ratio to clkin sensed 1 0 256 ratio to clkin sensed 1 1 256 fixed ? . = 256 fs ? sclk is master clock. clkin is not used. not available in multiplier slave sub-mode. table 4. sm3-s/sm3-ms, bits per frame. sclk to clkin ratio fs (khz) fs (khz) bpf bpf bpf with clkin with clkin or 16xclkin or 16xclkin 256 128 64 12.288 mhz 11.2896 mhz 1 2 4 48.00 44.10 1.5 3 6 32.00 29.40 2 4 8 24.00 22.05 2.5 5 10 19.20 17.64 3 6 12 16.00 14.70 4 8 16 12.00 11.025 5 10 20 9.60 8.82 6 12 24 8.00 7.35 table 5. sm3-s/sm3-ms, fs select. cs4218 20 ds135f1
ignored and the sample frequency is linearly scaled with sclk. (the clkin pin must be tied low.) this mode also fixes sclk at 256 bits per frame with mf7:sfs1 and mf8:sfs2 select- ing the particular sub-frame. this master clocking option is not available in the multiplier (sm3-ms) sub-mode. multiplier sub-modes (sm3-mm and sm3-ms) the sm3 multiplier sub-modes are identical to the sm3-m and sm3-s sub-modes with the fol- lowing exceptions: set smode1 = smode2 = smode3 = 0. this selects sm3 multiplier mode. clkin must be 16*fs, as opposed to 256*fs used for sm3-m and sm3-s. a 0.47uf capacitor must be connected to the filt pin as shown in figure 8. master / slave setup, frame formats, and sample rate selection are identical to sm3-m and sm3- s. please note that the mf1:f1 = mf2:f2 = 1 slave configuration supported by the sm3-s sub- mode it not available in sm3-ms sub-mode. sub-frame 1 frame (n+1) word a word b sub-frame 1 word a word b frame n 64 sclk periods frame (n+2) sub-frame 1 word a word b frame (n+3) sub-frame 1 word a word b ssync data sfs2 sfs1 frame 001 mf8: mf7: sub- figure 16. sm3-s and sm3-ms - 64 bpf; mf1:f1, mf2:f2 = 00 sub-frame 1 sub-frame 2 frame (n+1) word a word b word a word b sub-frame 1 word a word b frame n 128 sclk periods sub-frame 2 word a word b frame (n+2) sub-frame 1 word a word b ssync data sfs2 sfs1 frame 0 0 0 1 1 2 mf8: mf7: sub- figure 17. sm3-s and sm3-ms - 128 bpf; mf1:f1, mf2:f2 = 01 sub-frame 1 sub-frame 2 sub-frame 3 sub-frame 4 frame (n+1) word a word b word a word b word a word b word a word b frame n sub-frame 1 word a word b 256 sclk periods ssync data sfs2 sfs1 frame 0 0 1 1 0 1 0 1 1 2 3 4 mf8: mf7: sub- figure 18. sm3-s and sm3-ms - 256 bpf; mf1:f1, mf2:f2 = 10 cs4218 ds135f1 21
serial mode 4, (sm4) serial mode 4 is enabled by setting smode3 = 1. both master and slave sub- modes are available and are selected by setting the smode2 and smode1 pins as shown in table 6. in master sub-mode, the phase relation- ship between sclk/ssync and clkin is controlled to minimize digital noise coupling into the analog section. therefore, master sub- mode may yield slightly better noise performance than slave sub-mode. in slave sub-mode, sclk and ssync must be synchro- nous to clkin. in serial mode 4, the clkin frequency must be 256 times the highest sample frequency needed. sm4 differs from sm3 and sm5 in that sm4 splits the audio data from the control data, with the control data on an independent serial port. this reduces the audio serial bus bandwidth by half, providing an easier interface to low-cost dsps. the audio serial port sub-frame is illus- trated in figure 19 for sm4. master sub-mode (sm4) master sub-mode configures ssync and sclk as outputs from the cs4218. during power down, ssync and sclk are driven high im- pedance, and during reset they both are driven low. there are two sm4 master sub-modes. one allows 32 bits per frame and the other allows 64 bits per frame. as shown in table 6, the smode1 and smode2 pins select the particu- lar master sub-mode (as well as the slave sub-mode). when smode1 is set to zero, smode2 selects either master sub-mode with 32-bit frames, or slave sub-mode. smode1,smode2 = 00 selects master sub- mode where a frame = sub-frame = 32 bits. this sub-mode allows only one codec on the audio serial bus, with the first 16 bits being the left channel and the second 16 bits being the right channel. the appendix b section contains more information on low-cost implementations of this sub-mode. smode1 = 1 selects master sub-mode with a frame width of 64 bits. this sub-mode allows up to two codecs to occupy the same bus. smode2 is now used to select the particular time slot. if smode2 = 0 the codec selects time slot 1, which is the first 32 bits. if smode2 = 1 the codec selects time slot 2, which is the second 32 bits. smode1 smode2 sm4, sub-mode 0 0 master, 32 bpf 0 1 slave, 128/64/32 bpf 1 0 master, 64 bpf, ts1 1 1 master, 64 bpf, ts2 table 6. sm4 sub-modes. ssync sclk sdin sdout sub-frame 16 17 32 1 1 8 9 24 25 32 14 23 adc - left word msb lsb adc - right word msb lsb adc - left word msb adc - right word lsb dac - left word msb lsb dac - right word msb lsb dac - left word msb dac - right word lsb (slave) (master) figure 19. sm4-audio serial port, 32 bpf cs4218 22 ds135f1
in master sub-mode, multifunction pins mf6:f1, mf7:f2, and mf8:f3 select the sample fre- quency as shown in table 7. this table indicates how to obtain standard audio sample frequencies given one of two clkin frequencies: 12.288 mhz or 11.2896 mhz. other clkin fre- quencies may be used with the corresponding sample frequencies being clkin/n. a change in sample rate automatically initiates a calibration cycle. slave sub-mode (sm4) in sm4, slave sub-mode is selected by setting smode1,smode2 = 01. this mode configures ssync and sclk as inputs to the cs4218. these two signals must be externally derived from clkin. since the cs4218 has no control over the phase relationship of ssync and sclk to clkin, the noise performance in slave sub-mode may be slightly worse than when using master sub-mode. the cs4218 inter- nally sets the sample frequency by sensing the ratio of sclk to clkin; therefore, for a given clkin frequency, the sample frequency is se- lected by changing the sclk frequency. a change in sample rate automatically initiates a calibration cycle. table 9 shows the sample rates generated with two example clocks. sm4-slave allows up to four codecs to occupy the same audio serial port. table 8 lists the pin configurations required to set the serial audio port up for 32, 64, or 128 bits-per-frame (bpf). since each codec requires one sub-frame of 32 bits, 64 bits-per-frame allows up to two codecs to occupy the same audio serial port, and 128 bits-per-frame allows up to four codecs to occupy the same audio serial port. when set up for more than one codec on the bus, other pins are needed to select the particular time slot (ts) associated with each codec. mf8:sfs2 selects the time slot when in 64 bpf mode, and mf8:sfs2 and mf7:sfs1 select one of four time slots when in 128 bits-per-frame mode. ta- ble 8 lists the decoding for time slot selection. fs (khz) mf6: mf7: mf8: n with clkin f1 f2 f3 12.288 11.2896 mhz mhz 0 0 0 256 48.00 44.10 0 0 1 384 32.00 29.40 0 1 0 512 24.00 22.05 0 1 1 640 19.20 17.64 1 0 0 768 16.00 14.70 1 0 1 1024 12.00 11.025 1 1 0 1280 9.60 8.82 1 1 1 1536 8.00 7.35 table 7. sm4-master, fs select mf6: mf7: mf8: bits per time f1 sfs1 sfs2 frame slot (bpf) (ts) 000 32 1 001 reserved 010 64 1 011 64 2 100 128 1 110 128 2 101 128 3 111 128 4 table 8. sm4-slave, audio port bpf & ts select sclk to clkin ratio fs (khz) fs (khz) bpf bpf bpf with clkin with clkin 128 64 32 12.288 mhz 11.2896 mhz 2 4 8 48.00 44.10 3 6 12 32.00 29.40 4 8 16 24.00 22.05 5 10 20 19.20 17.64 6 12 24 16.00 14.70 8 16 32 12.00 11.025 10 20 40 9.60 8.82 12 24 48 8.00 7.35 table 9. sm4-slave, fs select. cs4218 ds135f1 23
serial control port (sm4) serial mode 4 separates the audio data from the control data. since control data such as gain and attenuation do not change often, this mode re- duces the bandwidth needed to support the audio serial port. the control information is entered through a separate port that can be asynchronous to the audio port and only needs to be updated when changes in the control data are needed. after a reset or power down, the control port must be written once to initialize it if the port will be ac- cessed to read or write control bits. this initial write is considered a "dummy" write since the data is ignored by the codec. a second write is needed to configure the codec as desired. then, the control port only needs to be written to when a change is desired, or to obtain the status infor- mation. the control port does not function if the master clock is not operating. when the control port is used asynchronously to the audio port, the noise performance may be slightly degraded due to the asynchronous digital noise. since control data does not need to be accessed each audio frame, an interrupt pin, mf5: int, is included in this mode and will go low when status has changed. the control port serial data format is illustrated in figure 20. the control port uses one of the multifunction pins as a chip select line, mf4: ccs, that must be low for en- tering control data. although only 23 bits contain useful data on mf2:cdin, a minimum of 31 bits must be written. if more than 31 bits are written without toggling mf4: ccs, only the first 31 are recognized. mf1:cdout contains status information that is output on the rising edge of mf3:cclk. status information is re- peated at the end of the frame, bits 25 through 30, to allow a simple 8-bit shift and latch register to store the most important status information using the rising edge of mf4: ccs at the latch control (see appendix b). interrupt pin - mf5: int serial mode 4 defines the multifunction pin mf5: int as an open-collector interrupt pin. in sm4, this pin requires a pullup resistor and will go low when the adv bit or di1 pin change, or a rising edge on the lcl or rcl bits occurs, or by exiting an sclk out of range condition (er- ror = 3). the interrupt may be masked by setting the mask bit in the control serial data port. mf5: int is reset by reading the control serial port. 16 17 32 mf4:ccs mf3:cclk 1 8 9 24 25 1 0 3 0 err version do1 mf2:cdin mf1:cdout 0 000 1 left a/d gain 3 0 right a/d gain 3 0 left d/a att. 40 right d/a att. 40 adv lcl rcl 10 err adv lcl rcl di1 00000000 di1 0 2 3 4 5 6 7 10 11 12 13 14 15 20 21 18 19 22 23 31 27 28 26 29 30 isl isr mute mask figure 20. sm4 - control serial port cs4218 24 ds135f1
serial mode 5 (sm5) the serial mode 5 is compatible with the phil- lips i 2 s serial protocol. sm5 is enabled by setting smode3 = 0, smode2 = 0, and smode1 = 1. this is a master mode fixed at 64 bpf. figure 21 shows the frame format of the sm5. figure 22 shows the detailed frame format. the multi-function pins mf4, mf7, and mf8 are not used in this mode. mf4 should be tied to vd, and mf7 and mf8 should be tied to ground. figures 11 & 12 illustrate the serial data in, sdin, and serial data out, sdout, sub-frames for sm5. sample frequency selection the multifunction pins mf1:f1, mf2:f2, and mf3:f3 are used to select the sample frequency divider. table 3 lists the decoding for the sample frequency select pins where the sample fre- quency selected is clkin/n. also shown are the sample frequencies obtained by using one of two example master clocks. a change in sample rate will automatically initiate a calibration cycle. word a word b frame n 64 sclk periods word a word b frame (n+1) word a word b frame (n+2) word a word b frame (n+3) word a word b frame (n+4) ssync data 1 sclk figure 21. serial mode 5 msb sclk ssync msb 32 clocks 32 clocks lsb word a word b lsb sdin sdout lsb frame figure 22. detailed serial mode 5. cs4218 ds135f1 25
power supply and grounding the cs4218, along with associated analog cir- cuitry, should be positioned in an isolated section of the circuit board, and have its own, separate, ground plane. on the cs4218, the analog and digital grounds are internally connected; there- fore, the agnd and dgnd pins must be externally connected with no impedance between them. the best solution is to place the entire chip on a solid ground plane as shown in fig- ure 23. preferably, it should also have its own power plane. the +5v (or +3.3v) supply must be connected to the cs4218 via a ferrite bead, positioned closer than 1" to the device. if using +5v for vd, the va supply can be derived from vd, as shown in figure 8. alternatively, a sepa- rate +5v analog supply may be used for va, in which case, the 2.0 w resistor between va and vd should be removed. a single connection be- tween the cs4218 ground (analog ground) and the board digital ground should be positioned as shown in figure 23. figure 24 illustrates the optimum ground and de- coupling layout for the cs4218 assuming a surface-mount socket and leaded decoupling ca- pacitors. surface-mount sockets are useful since the pad locations are identical to the chip pads; therefore, assuming space for the socket is left on the board, the socket can be optional for pro- duction. figure 24 depicts the top layer, containing signal traces, and assumes the bottom or inter-layer contains a fairly solid ground plane. the important points are that there is solid ground plane under the codec on the same layer as the codec and it connects all ground pins with thick traces providing the absolute lowest imped- ance between ground pins. the decoupling capacitors are placed as close as possible to the device which, in this case, is the socket bound- ary. the lowest value capacitor is placed closest to the codec. vias are placed near the agnd and dgnd pins, under the ic, and should attach to the solid ground plane on another layer. the negative side of the decoupling capacitors should also attach to the same solid ground plane. traces and vias bringing power to the codec should be large, which minimizes the impedance. although not shown in the figures, the trace lay- ers (top layer in the figures) should have ground plane fill in-between the traces to minimize cou- pling into the analog section. if using all surface-mount components, the de- coupling capacitors should be placed on the same layer as the codec and in the positions shown in figure 25. the vias shown are as- sumed to attach to the appropriate power and ground layers. traces and vias bringing power to the codec should be as large as possible to mini- mize the impedance. if using a through-hole socket, effort should be made to find a socket with minimum height, which will minimize the socket impedance. when using a through hole socket, the vias un- der the codec in figure 24 and 25 are not needed since the pins serve the same function. cs4218 26 ds135f1
digital ground plane note that the cs4218 is oriented with its digital pins towards the digital end of the board. cpu & digital logic codec digital signals codec analog signals & components > 1/8" cs4218 power connection use ferrite bead ground connection analog ground plane figure 23. cs4218 board layout guideline 1 1.0 uf 0.1 uf 10 uf + 1.0 uf 0.1 uf 0.1 uf + + analog supply digital supply figure 24. cs4218 decoupling layout guideline cs4218 ds135f1 27
1 1.0 uf 0.1 uf 10 uf + 1.0 uf 0.1 uf 0.1 uf + + analog supply digital supply figure 25. cs4218 surface mount decoupling layout cs4218 28 ds135f1
pin descriptions 40 42 34 36 38 6 2 4 8 10 1 3 5 7 9 11 23 25 27 29 31 33 28 24 26 30 32 44 12 14 16 18 20 22 sm mf1 mf2 mf3 mf4 mf5 mf6 mf7 mf8 sm5 f1 f2 f3 tie to vd do2 di2 tie to dgnd tie to dgnd 3-sl f1 f2 di3 ma do2 di2 sfs1 sfs2 3-ma f1 f2 f3 ma do2 di2 sfs1 sfs2 4-sl cdout cdin cclk ccs int f1 sfs1 sfs2 4-ma cdout cdin cclk ccs int f1 f2 f3 ssync reset sclk clkin sdout vd sdin dgnd smode3 filt mf1:f1/cdout nc mf2:f2/cdin nc mf5:do2/int nc do1 nc mf4:ma/ccs nc mf3:di3/f3/cclk nc mf6:di2/f1 pdn di1 nc smode2 rout mf7:sfs1/f2 lout mf8:sfs2/f3 nc smode1 nc lin2 nc lin1 refbuf rin2 refbyp rin1 refgnd va agnd cs4218 44-pin tqfp (q) top view cs4218 ds135f1 29
power supply vd - digital supply, pin 4(l), 42(q). +5v or +3.3v digital supply. va - analog +5v supply, pin 24(l), 18(q). +5v analog supply. dgnd - digital ground, pin 5(l), 43(q). digital ground. must be connected to agnd with zero impedance. cs4216 44-pin plcc (l) top view ssync reset sclk clkin sdout vd sdin dgnd smode3 filt mf1:f1/cdout nc mf2:f2/cdin nc mf5:do2/int nc do1 nc mf4:ma/ccs nc mf3:di3/f3/cclk nc mf6:di2/f1 pdn di1 nc smode2 rout mf7:sfs1/f2 lout mf8:sfs2/f3 nc smode1 nc lin2 nc lin1 refbuf rin2 refbyp rin1 refgnd va agnd cs4218 44-pin plcc (l) top view 18 20 22 24 26 28 1 2 4 640 42 44 12 8 10 14 16 7 9 11 13 15 17 29 31 33 35 37 39 34 30 32 36 38 sm mf1 mf2 mf3 mf4 mf5 mf6 mf7 mf8 sm5 f1 f2 f3 tie to vd do2 di2 tie to dgnd tie to dgnd 3-sl f1 f2 di3 ma do2 di2 sfs1 sfs2 3-ma f1 f2 f3 ma do2 di2 sfs1 sfs2 4-sl cdout cdin cclk ccs int f1 sfs1 sfs2 4-ma cdout cdin cclk ccs int f1 f2 f3 cs4218 30 ds135f1
agnd - analog ground, pin 23(l), 17(q). analog ground. must be connected to dgnd with zero impedance. analog inputs rin1 - right input #1, pin 25(l), 19(q). right analog input #1. full scale input, with no gain, is 1vrms, centered at refbuf. rin2 - right input #2, pin 26(l), 20(q). right analog input #2. full scale input, with no gain, is 1vrms, centered at refbuf. lin1 - left input #1, pin 27(l), 21(q). left analog input #1. full scale input, with no gain, is 1vrms, centered at refbuf. lin2 - left input #2, pin 28(l), 22(q). left analog input #2. full scale input, with no gain, is 1vrms, centered at refbuf. analog outputs rout - right channel output, pin 15(l), 9(q). right channel analog output. maximum signal is 1 vrms centered at refbuf. lout - left channel output, pin 16(l), 10(q). left channel analog output. maximum signal is 1 vrms centered at refbuf. refbyp - analog reference decoupling, pin 21(l), 15(q). a 10 m f and 0.1 m f capacitor must be attached between refbyp and refgnd. refgnd - analog reference ground connection, pin 22(l), 16(q). connect to agnd. refbuf - buffered reference out, pin 20(l), 14(q). a nominal +2.1v output for setting the bias level for external analog circuits. serial digital audio interface signals sdin - serial port data in, pin 42(l), 36(q). digital audio data to the dacs and level control information is received by the cs4218 via sdin. sdout - serial port data out, pin 43(l), 37(q). digital audio data from the adcs and status information is output from the cs4218 via sdout. sclk - serial port bit clock, pin 44(l), 38(q). sclk controls the digital audio data on sdout and latches the data on sdin. sclk must be synchronous to the master clock. cs4218 ds135f1 31
ssync - serial port sync signal, pin 1(l), 39(q). indicates the start of a digital audio frame. ssync must be synchronous to the master clock. smode1 - serial mode select, pin 29(l), 23(q). one of three pins that select the serial mode and function of the multifunction pins. smode2 - serial mode select, pin 32(l), 26(q). one of three pins that select the serial mode and function of the multifunction pins. smode3 - serial mode select, pin 41(l), 35(q). one of three pins that select the serial mode and function of the multifunction pins. multifunction digital pins mf1:f1 - format bit 1 in sm3 and sm5, pin 40(l), 34(q). in sm3-m, sm3-mm, and sm5, this pin is a format bit and is used as one of three sample frequency select pins, or as one of two bits-per-frame select pins when in sm3-s or sm3-ms. mf1:cdout - control data output in sm4, pin 40(l), 34(q). in serial mode 4 this pin is the data output for the control port which contains status information. mf2:f2 - format bit 2 in sm3 and sm5, pin 39(l), 33(q). in sm3-m, sm3-mm, and sm5, this pin is a format bit and is used as one of three sample frequency select pins , or as one of two bits-per-frame select pins when in sm3-s or sm3-ms. mf2:cdin - control data input in sm4, pin 39(l), 33(q). in sm4 this pin is the control port data input which contains data such as gain and attenuation settings as well as input select, mute, and digital output bits. mf3:f3 - format bit 3 in sm3 and sm5, pin 35(l), 29(q). in sm3-m, sm3-mm, and sm5, this pin is a format bit and is used as one of three sample frequency select pins. in sm3-s and sm3-ms, the pin reverts to being a general purpose input. mf3:cclk - control data clock in sm4, pin 35(l), 29(q). in sm4 this pin is the control port serial bit clock which latches data from cdin on the falling edge, and outputs data onto cdout on the rising edge. mf4:ma - master sub-mode in sm3, pin 36(l), 30(q). in sm3, this pin selects either master or slave sub-modes. when mf4:ma = 1, the codec is in master sub-modes and outputs ssync and sclk. when mf4:ma = 0, the codec is in slave sub-modes and receives ssync and sclk from an external source that must be frequency locked to clkin. mf4 - sm5, pin 36(l), 30(q). in sm5, this pin is not used and should be tied to vd. cs4218 32 ds135f1
mf4: ccs - control data chip select in sm4, pin 36(l), 30(q). in sm4 this pin is the control port chip select signal. when low, the control port data is clocked in cdin and status data is output on cdout. when ccs goes high, control data is latched internally. this data remains active until new data is clocked in. the control port may also be asynchronous to the audio data port. mf5:do2 - parallel digital bit output #2 in sm3 and sm5, pin 38(l), 32(q). in sm3 and sm5, this pin reflects the value of the do2 bit in the sub-frame. mf5: int - interrupt in sm4, pin 38(l), 32(q). in sm4 this pin is an active low interrupt signal that is maskable using the msk bit in the control port serial data stream. int is an open-collector output and requires and external pull-up resistor. assuming the mask bit is not set, and interrupt is triggered by a change in adv or di1, or a rising edge on lcl or rcl, or when exiting an sclk out of range condition (error = 3) mf6:di2 - parallel digital bit input #2 in sm3 and sm5, pin 34(l), 28(q). in sm3 and sm5, this pin value is reflected in the di2 bit of the sub-frame. mf6:f1 - format bit 1 in sm4, pin 34(l), 28(q). in sm4 this pin is a format bit and is used as one of three sample frequency select pins when in master mode. in slave mode, mf6:f1 is used to determine the number of sub-frames within a frame. mf7:sfs1 - sub-frame select 1 in sm3/sm4-sl, pin 31(l), 25(q). in sm3, mf7:sfs1 helps select the sub-frame that this particular cs4218 is allocated. in slave sub-mode of sm4, this pin is one of two pins used as a sub-frame select when mf6:f1 = 1 (128-bit frames). when mf6:f1 = 0, this pin is used to select the frame sizes of 32 or 64 bits. mf7 - sm5, pin 31(l), 25(q). in sm5, this pin is not used and should be tied to dgnd. mf7:f2 - format bit 2 in sm4-ma, pin 31(l), 25(q). in master sub-mode of sm4, this pin is used as one of three sample frequency select pins. mf8:sfs2 - sub-frame select 2 in sm3/sm4-sl, pin 30(l), 24(q). in sm3 and slave sub-mode of sm4, mf8:sfs2 helps select the sub-frame that this particular cs4218 is allocated. mf8 - sm5, pin 30(l), 24(q). in sm5, this pin is not used and should be tied to dgnd. mf8:f3 - format bit 3 in sm4-ma, pin 30(l), 24(q). in master sub-mode of sm4, this pin is a format bit and is one of three sample frequency select pins. cs4218 ds135f1 33
miscellaneous reset - reset input, pin 2.(l), 40(q). resets the cs4218 to a known state, and must be initiated after power-up or power-down mode. releasing reset causes the cs4218 to initiate a calibration sequence. the cs4218 automatically initiates a calibration sequence after a sample rate change in master and slave modes. clkin - master clock, pin 3(l), 41(q). clkin is the master clock that operates the internal logic. clkin is 256 fs max , where fs max is the highest sample frequency needed, for sm3 master and slave, and for sm4 master and slave. clkin is 16xfs max in sm3 multiplier sub-modes. different sample frequencies are obtained by either changing the ratio of sclk to clkin in slave modes, or changing the format pin values (f2-f0) in master modes. pdn - power down, pin 13(l), 7(q). this pin, when low, causes the cs4218 to go into a power down state. reset should be held low for 50 ms when exiting the power down state to allow time for the voltage reference to settle. di1 - parallel digital bit input #1, pin 33(l), 27(q). this pin value is reflected in the di1 bit in the sub-frame. do1 - parallel digital bit output #1, pin 37(l), 31(q). this pin reflects the value of the do1 bit in the sub-frame filt - pll filter, pin 6(l), 44(q). this pin should have the 0.47 m f pll loop filter capicator connected when using sm3 multiplier sub-modes. when using sm3-m, sm3-s, sm4, or sm5 modes, this pin should be left floating. this pin has an internal pull-down making the cs4218 pin compatible with the cs4216 operating in serial modes sm3-m, sm3-s, and sm4. nc - no connection, pins 7, 8, 9, 10, 11, 12, 14, 17, 18, 19(l) pins 1, 2, 3, 4, 5, 6, 8, 11, 12, 13(q). these pins should be left floating with no trace attached to allow backwards compatibility with future revisions. they should not be used as a convenient path for signal traces. cs4218 34 ds135f1
package dimensions b a a b 1 g h i k j 0.102 max lead coplanarity l m de n c f 44 pin quad flatpack millimeters min max 11.75 9.90 0 0.80 bsc 0.35 bsc 12 0.54 0.54 1.35 0.05 1.60 0.17 2 0.35 12.25 10.10 7 0.74 0.74 1.50 10 0.65 b c d e dim f g h i j k a l m n inches max 12 0.063 0.007 0.482 0.398 7 0.029 0.029 0.059 10 0.026 min 0.390 0 0.021 0.021 0.053 0.002 2 0.014 0.463 0.031 bsc 0.014 bsc o ooo o o oo o o 44 pin tqfp 1.4 mm package thickness all dimensions are in millimeters and parenthetically in inches. 0.25 (0.010) r max 1.35 (0.053) 1.19 (0.047) a b b a 1.14 (0.045) x 45deg. nom no. of terminals min max min max min max a b c 3 nom 0.46 ( 0.018 ) 0.33 ( 0.013 ) c 3 nom 4.62 (0.182) 4.11 (0.162) 1.14 (0.045) 0.63 (0.025) 2.41 (0.095) 1.27(0.050) min x45deg.nom 44 17.40 17.65 16.51 16.66 14.98 16.00 (0.685) (0.695) (0.650) (0.656) (0.590) (0.630) 44 pin plcc cs4218 ds135f1 35
parameter definitions resolution the number of bits in the input words to the dacs, and in the output words from the adcs. differential nonlinearity the worst case deviation from the ideal codewidth. units in lsb. total dynamic range tdr is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor. it is measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e. attenuation bits for the dacs at full attenuation). units in db. instantaneous dynamic range idr is the ratio of a full-scale rms signal to the rms noise available at any instant in time, without changing the input gain or output attenuation settings. it is measured using s/(n+d) with a 1 khz, -60 db input signal, with 60 db added to compensate for the small input signal. use of a small input signal reduces the harmonic distortion components to insignificance when compared to the noise. units in db. total harmonic distortion thd is the ratio of the rms value of a signals first five harmonic components to the rms value of the signals fundamental component. thd is calculated using an input signal which is 3db below typical full-scale, and is referenced to typical full-scale. interchannel isolation the amount of 1 khz signal present on the output of the grounded input channel, with 1 khz 0 db signal present on the other channel. units in db. interchannel gain mismatch for the adcs, the difference in input voltage that generates the full scale code for each channel. for the dacs, the difference in output voltages for each channel with a full scale digital input. units in db. frequency response worst case variation in output signal level versus frequency over the passband. tested over the frequency band of 10 hz to 20 khz, with the sample frequency of 48 khz. units in db. step size typical delta between two adjacent gain or attenuation values. units in db. absolute gain/attenuation step error the deviation of a gain or attenuation step from a straight line passing through the no-gain/attenuation value and the full-gain/attenuation value (i.e. end points). units in db. offset error for the adcs, the deviation of the output code from the mid-scale with the selected input at refbuf. for the dacs, the deviation of the output from refbuf with mid-scale input code. units in lsbs for the adcs and volts for the dacs. cs4218 36 ds135f1
out of band energy the ratio of the rms sum of the energy from 0.46 fs to 2.1 fs compared to the rms full-scale signal value. tested with 48 khz fs giving a out-of-band energy range of 22 khz to 100 khz. cs4218 ds135f1 37
appendix a: cs4218 compatibility with cs4216 important !! if you are upgrading your design from the cs4216 to the cs4218, please make sure to read this entire appendix. the cs4218 is pin compatible with the cs4216. this appendix provides a summary of differences between the two codecs. pin compatibility the cs4218 is 100% pin compatible with the cs4216 when used in serial modes 3 and 4. the differences are noted in the following paragraphs and tables. the cs4218 integrates the 600-ohm series resistors for the lout and rout analog outputs on the ic itself. for the cs4216, these resistors are not on-chip, and need to be provided externally. the cs4218 pin named smode3 does not incorporate an on-chip pull-down resistor, as is provided on the cs4216 rev b and later. this pin must be tied high or low, or driven by control logic to the desired state (depends on the serial mode used). if this pin is left floating, the codec will not work correctly. the cs4218 adds the pin named filt. on the cs4216, this pin is a no connect. the filt pin is only used when employing the sm3 multiplier sub-mode. when using this sub-mode, a 0.47uf capacitor must be connected from the filt pin to agnd. when not using the multiplier sub-mode, this pin may remain unconnected. serial modes the cs4218 supports serial modes 3 and 4 of the cs4216. in addition, the cs4218 provides the sm3 multiplier sub-mode and serial mode 5, which are not provided on the cs4216. the cs4218 does not support serial modes 1 and 2 of the cs4216. decimation and interpolator filter responses the cs4218 and cs4216 use different digital filters for the adc decimators and dac interpolators. tables a1 and a2 provide a comparison between each codecs filter responses. cs4218 38 ds135f1
parameter units cs4218 cs4216 passband hz 0-0.4fs 0-0.45fs passband ripple db 0.1 0.2 transition band hz 0.4-0.6fs 0.45-0.55 stop band hz 0.6fs 0.55fs stop band rejection db 74db 80db group delay sec 8/fs 16/fs table a1: decimation filter comparison parameter units cs4218 cs4216 passband hz 0-0.4fs 0-0.45fs passband ripple db 0.1 0.1 transition band hz 0.4-0.6fs 0.45-0.55 fs stop band hz 0.6fs 0.55fs stop band rejection db 74db 74db group delay sec 8/fs 16/fs table a2: interpolation filter comparison digital power supplies and input logic levels the cs4218 and cs4216 both require that the analog power supply be 5v +/- 0.25v. the cs4218 digital power supply can operate from 5v +/- 0.25v and 3.3v +/- 0.3v. when operated from a 5v supply, the cs4218 is ttl and cmos compatible inputs & outputs. when operated from a 3.3v power supply, the cs4218 is lvttl and lvcmos compatible. in comparison, the cs4216 operates from a 5v +/- 0.25v power supply. it provides only cmos logic level inputs. the cs4216 requires level-translation logic (using the 74hct family) when interfacing its inputs with ttl logic. cs4218 ds135f1 39
appendix b: applications of sm4 figure b1 illustrates one method of using serial mode 4 wherein a dsp controls the audio serial port and a microcontroller controls the control port. each controller is run independently and the micro updates the control information only when needed, or when an interrupt from the cs4218 occurs. figure b2 illustrates the minimum interface to the cs4218. in this application, the dsp sends and receives stereo dac and adc information. the cs4218 is configured for 32 bits per frame, master sub-mode. the control data resets to all zeros, which configures the cs4218 as a simple stereo codec: no gain, no attenuation, line inputs #1, and dac outputs not muted. figure b3 illustrates how to use all the cs4218 features with a low cost dsp that cannot support the interrupt rate of sm3. using sm4 (32 bits per frame, master sub-mode) reduces the dsp interrupts in half since the control data is split from the audio data. this circuit is comprised of three independent sections which may individually be eliminated if not needed. micro- controller serial port general purpose port pins irq dsp sdout sdin ssync sclk cs4218 mf1:cdout mf2:cdin mf4:ccs mf3:cclk reset mf8:f3 mf7:f2 mf6:f1 mf5:int sm4 vd+ 43 42 1 44 40 39 36 35 38 2 34 31 30 figure b1. sm4 - microcontroller interface dsp sdout sdin ssync sclk cs4218 mf1:cdout mf2:cdin mf4:ccs mf3:cclk mf5:int sm4 vd+ reset mf8:f3 mf7:f2 mf6:f1 hard wired or dip switch selectable 32 bpf 43 42 1 44 35 36 38 40 39 2 34 31 30 figure b2. sm4 - minimum dsp interface cs4218 40 ds135f1
dsp sdout sdin ssync sclk cs4218 mf1:cdout mf2:cdin mf4:ccs mf3:cclk reset mf8:f3 mf7:f2 mf6:f1 hc574 hc595 sclk lclk ain a b c d e f g h 0 adv di1 rcl lcl err0 err1 1 hc597 hc597 hc597 dout load din cs^fs oe cs^status cs^control 24+ bit dsp data bus mf5:int sm4 32 bpf vd+ 43 42 1 44 35 36 38 39 40 2 34 31 30 figure b3. sm4 - enhanced dsp interface cs4218 ds135f1 41
to load control data into the codec, three hc597s are utilized. these are the latches that store the dsp-sent control data, and shift registers that shift the data into the codec. the codec uses an inverted ssync signal to copy the latches to the shift registers every frame. in this diagram the dsp is as- sumed to have a data bus bandwidth of at least 24 bits. if the dsp has less than 24-bits, the three hc597s must be split into two addresses. since the hc597 internal latches are copied to the shift registers, the latches continually hold the dsp-sent data; therefore, the dsp only needs to write data to the latches when a change is desired. the second section is comprised of an hc595 shift register and latch that is clocked by an inverted sclk. the data shifted into the hc595 is transferred to the hc595s latch by the ssync signal. this hc595 captures the 8 bits prior to the ssync signal (which is also mf4: ccs) going high. as shown in figure 12, and assuming the mf4: ccs (ssync) signal rises at bit 32, the 8-bits prior to mf4: ccs rising are a copy of all the important status bits. this allows one shift register to capture all the important information. the interrupt pin cannot reliably be used in this configuration since the interrupt pin is cleared by reading the control port which occurs asynchronously (every audio frame) with re- spect to the interrupt occurrence. the third section is only needed if sample frequencies need to be changed. this section is comprised of an hc574 octal latch that can be replaced by general purpose port pins if available. this section controls the sample frequency selection bits: mf6:f1, mf7:f2, mf8:f3 and the reset pin. a change in sample rate automatically initiates a calibration cycle. cs4218 42 ds135f1
appendix c: setting clkin/sclk ratio for desired sample rate in slave sub-modes, the cs4218 detects the ratio between the clkin and sclk rates and sets the internal sample rate accordingly. the following formula can be used to determine the ratio of clkin to sclk for any desired sample rate for both serial modes 3 and 4, slave sub-modes. clkin sclk = ( 256 fsmax ) ( bpf fs ) where: clkin = master clock input in sm3 multiplier slave sub-mode, clkin is replaced by 16* clkin. sclk = serial port bit clock. fsmax = maximum system sample rate. fs = desired sample rate. bpf = the number of bits per frame (256, 128, 64 or 32) example 1 : sm3-s, fsmax = 48 khz, fs = 8 khz, bpf = 64 clkin sclk = ( 256 48000 ) ( 64 8000 ) = 12.288 mhz 512 khz = 24 example 2 : sm4-s, fsmax = 8 khz, fs = 8 khz, bpf = 32 clkin sclk = ( 256 8000 ) ( 32 8000 ) = 2.048 mhz 256 khz = 8 cs4218 ds135f1 43
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